Method for manufacturing flash memory cell of split gate type

专利摘要:
PURPOSE: A method for manufacturing a flash memory cell of split gate type is provided to reduce a damage of a semiconductor substrate due to a stress when forming a field oxide layer, to prevent a bridge between floating gates from being generated, to improve a reliability of components by improving insulation capability between electrodes, to obtain high density of components. CONSTITUTION: A method for manufacturing a flash memory cell of split gate type includes a first through fifth steps. The first step is to pattern a first polysilicon layer by using a first mask layer after sequentially forming a tunnel oxide layer(34), the first polysilicon layer on a semiconductor substrate(31) on which a field oxide layer(32) is already formed. The second step is to delete the first mask layer, to sequentially forming a dielectric layer(36), a second polysilicon layer and a top oxide layer(38) on the overall semiconductor substrate, to form a control gate by sequentially deleting the top oxide film, the second polysilicon layer and the dielectric layer by using the second mask layer, and to expose a part of the first polysilicon layer pattern. The third step is to form a source and a drain area by using ion injection process after etching the exposed area of the field oxide layer and the tunnel oxide layer. The fourth step is to form a floating gate and to define a channel area of a select gate by etching the exposed portion of the first polysilicon layer pattern by using the second mask layer. The fifth step is to sequentially forming an insulating layer, select gate oxide layer and select gate after deleting the second mask layer.
公开号:KR20000021378A
申请号:KR1019980040404
申请日:1998-09-28
公开日:2000-04-25
发明作者:홍성훈；이희기；임일호
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

Manufacturing Method of Split-Gate Flash Memory Cell
The present invention relates to a method of manufacturing a split gate type flash memory cell, and more particularly, to a method of manufacturing a split gate type flash memory cell capable of improving integration and reliability.
In general, a flash memory cell has an electric program and erase function, and is a kind of nonvolatile memory cell capable of permanently preserving programmed data. These flash memory cells have recently been increasing in density, and as the degree of integration has increased, the field of application has also expanded. Such a flash memory cell is divided into a stack gate type and a split gate type according to the type of the gate electrode. Here, the split gate type flash memory cell will be described.
Conventional split gate type flash memory cells form a field oxide layer to define an active region, and a floating gate polysilicon layer remains in the active region using a floating gate mask (two sides of the floating gate are defined), and the control The gate mask is used to form the control gate and the floating gate (self-aligned, the remaining two sides are defined), the source / drain mask is used to form the source / drain, and the select gate mask is then used to select gate. It is prepared through the process of forming.
In the above, the floating gate is completed through a mask for the floating gate and a mask for the control gate. When misalignment occurs during the mask for the floating gate or the mask for the control gate, the floating gate is self-aligned during the mask for the control gate. The polysilicon layer for etching the floating gate is not completely etched to cause a bridge phenomenon. To prevent this, it is necessary to increase the design rule or reduce the process margin of the mask for the floating gate and the process margin of the mask for the control gate. In this case, high integration of the device is difficult.
In addition, in order to solve the bridge phenomenon of the floating gate, the shape of the control gate is bent at the portion overlapping with the floating gate. In this case, the insulating characteristics of the floating gate and the select gate are overlapped at the portion overlapping with the field oxide layer. The problem of deterioration arises.
On the other hand, when the field region is defined as a plurality of isolation forms, a large portion of damage occurs in the semiconductor substrate of the active region due to the stress caused by the oxidation process for forming the field oxide film, thereby reducing the reliability of the device. Will act as.
Accordingly, the present invention can reduce the damage of the semiconductor substrate due to the stress when forming the field oxide film, prevent the bridge-to-floating bridge phenomenon, secure the electrical insulation between the electrodes to improve the reliability of the device, while achieving high integration of the device It is an object of the present invention to provide a method of manufacturing a split gate flash memory cell.
In order to achieve the above object, the method of manufacturing a split gate flash memory cell of the present invention sequentially forms a tunnel oxide film and a first polysilicon layer on a semiconductor substrate on which a field oxide film is formed, and then uses the first mask layer. Patterning a first polysilicon layer, removing the first mask layer, and sequentially forming a dielectric film, a second polysilicon layer, and a top oxide film on an entire structure, and using the second mask layer to form the top oxide film, Sequentially etching the second polysilicon layer and the dielectric layer, thereby forming a control gate, exposing a portion of the first polysilicon layer pattern, and etching the exposed portions of the field oxide layer and the tunnel oxide layer. Forming a source and a drain region by an ion implantation process, and using the second mask layer to form the first polysilicon. Etching the exposed portion of the layer pattern, thereby forming a floating gate, defining a channel region of the select gate, removing the second mask layer, and then sequentially forming an insulating film, a select gate oxide film, and a select gate. Characterized in that it comprises a step.
1 to 4 are layout and cross-sectional views sequentially illustrating a method of manufacturing a split gate type flash memory cell according to the present invention.
<Description of Signs of Major Parts of Drawings>
31 semiconductor substrate 32 field oxide film
34 tunnel oxide film 35 polysilicon layer for floating gate (floating gate)
36 dielectric layer 37 polysilicon layer for control gate (control gate)
38: top oxide film 39: source region
40: drain region 41: oxide film
42 spacer insulating film 43 select gate oxide film
44 polysilicon layer for select gate (select gate)
50 mask layer for floating gate 60 mask layer for control gate
Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
1 to 4 are layouts and cross-sectional views sequentially illustrating a method of manufacturing a split gate type flash memory cell according to the present invention, and FIG. 4A illustrates a layout of the split gate type flash memory cell according to the present invention. It is shown by the process step, (b) of each figure is sectional drawing which shows the state which AA line cut out of each figure (a), and (c) of each figure has cut out the BB line of each figure (a). It is sectional drawing which shows the state.
Referring to FIG. 1, after forming a linear field oxide film 32 on a semiconductor substrate 31 to define an active region, a tunnel oxide film 34 and a polysilicon layer 35 for floating gate are sequentially formed. . The floating gate mask layer 50 is formed on the floating silicon polysilicon layer 35 to cover the region where the floating gate is to be formed as well as the region where the channel of the select gate is to be formed. The floating gate polysilicon layer 35 is etched by a poly etching process using the floating gate mask layer 50, thereby expanding the floating gate polysilicon layer 35 to a portion where the channel of the select gate is formed. Will remain.
In the above, the field oxide film 32 is formed in a straight line shape in order to minimize the stress portion of the active region due to the oxidation process. By etching the floating gate polysilicon layer 35 using the floating gate mask layer 50, portions at which three sides of the floating gate and source / drain regions are to be formed are defined.
Referring to FIG. 2, after removing the floating gate mask layer 50, the dielectric film 36 and the control gate polysilicon layer 37 are formed on the entire structure including the first-etched floating gate polysilicon layer 35. ) And top oxide film 38 are sequentially formed. The control gate mask layer 60 is formed on the top oxide film 38. The control gate 37, the source region 39, the drain region 40, and the floating gate 35 are sequentially formed using the control gate mask layer 60.
In the above, the control gate mask layer 60 intersects with the field oxide layer 32 while covering the region where the floating gate of the primary-etched floating polysilicon layer 35 is to be formed, and forms a straight line. The top oxide film 38, the control gate polysilicon layer 37, and the dielectric film 36 are sequentially etched by the etching process using the control gate mask layer 60, and thus, the straight control gate 37 ) Is completed, and a part of the first-etched floating polysilicon layer 35, that is, the floating gate polysilicon layer 35 in the region where the select gate channel is to be formed is exposed. The exposed portion of the field oxide layer 32 and the exposed portion of the tunnel oxide layer 34 are exposed by a self-aligned etching process using the exposed portions of the control gate mask layer 60 and the floating gate polysilicon layer 35 as an etching mask. The portion is etched, thereby exposing the semiconductor substrate 31 in the region where the source / drain regions are to be formed. Then, impurity ions are implanted into the exposed portions of the semiconductor substrate 31 by a self-aligned ion implantation process using the exposed portions of the control gate mask layer 60 and the floating gate polysilicon layer 35 as ion implantation barriers. The source region 39 and the drain region 40 are thus formed.
Referring to FIG. 3, an exposed portion of the polysilicon layer 35 for the floating gate is removed by an etching process using the mask layer 60 for the control gate, whereby the floating gate 35 is completed to form a floating gate ( A stack gate of 35 and a control gate 37 is formed, and a portion of the field oxide film 32 and a semiconductor substrate 31 in a region where a channel of the select gate is to be formed are exposed.
Referring to FIG. 4, after performing the process of removing the control gate mask layer 60 and the poly oxidization process, spacer spacers 42 are formed on both sides of the stack gate. The select gate oxide film 43 is formed through an oxidation process, wherein the oxide film 41 is formed thick on the source region 39 and the drain region 40 into which the impurity ions are implanted. After forming the select gate polysilicon layer 44 on the entire structure including the gate oxide layer 43, the select gate polysilicon layer 44 is patterned to cross the control gate 37 while passing over the stack gate. The select gate 44 is formed.
As described above, according to the present invention, by forming the field oxide film and the polysilicon layer for the control gate in a straight line shape, the process margin and the integration degree of the device can be improved, the bridge phenomenon of the floating gate can be prevented, and the floating gate and Insulation between the select gates can be increased. In addition, a turn around time may be reduced by forming a control gate, a floating gate, and a source / drain region using a mask for a control gate.

权利要求:
Claims (4)
[1" claim-type="Currently amended] Sequentially forming a tunnel oxide film and a first polysilicon layer on the semiconductor substrate on which the field oxide film is formed, and then patterning the first polysilicon layer using a first mask layer;
After removing the first mask layer, a dielectric film, a second polysilicon layer, and a top oxide film are sequentially formed on the entire structure, and the top oxide film, the second polysilicon layer, and the dielectric film are sequentially formed using a second mask layer. Etching, thereby forming a control gate, exposing a portion of the first polysilicon layer pattern;
Etching the exposed portions of the field oxide film and the tunnel oxide film, and then forming source and drain regions by an ion implantation process;
Etching the exposed portion of the first polysilicon layer pattern using the second mask layer, thereby forming a floating gate, and defining a channel region of the select gate;
And removing the second mask layer, and then sequentially forming an insulating film, a select gate oxide film, and a select gate.
[2" claim-type="Currently amended] 2. The method of claim 1, wherein the field oxide layer is formed in a straight line shape.
[3" claim-type="Currently amended] The split gate type flash memory cell of claim 1, wherein the first mask layer is formed on the first polysilicon layer to cover a region where a floating gate is to be formed as well as a region where a channel of the select gate is to be formed. Manufacturing method.
[4" claim-type="Currently amended] The method of claim 1, wherein the source and drain regions are formed using an exposed portion of the first polysilicon layer pattern and the second mask layer as an ion implantation barrier.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1998-09-28|Application filed by 김영환, 현대전자산업 주식회사

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1998-09-28|Priority to KR1019980040404A

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2000-04-25|Publication of KR20000021378A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019980040404A|KR20000021378A|1998-09-28|1998-09-28|Method for manufacturing flash memory cell of split gate type|